This disclosure relates generally to very high data-rate communication systems, e.g., employing a receiver for high speed digital communications signals and a phase interpolator, and more particularly to a novel phase interpolation calibration technique employing linear phase interpolator architecture.
Phase Interplolators, also referred to as Phase Rotators, are an integral part of a clock-data recovery (CDR) module in a very high data-rate communication system, e.g., like Serial Deserial or “SerDes” links. A Phase Interplolator generates finely phase shifted versions of the data sampling clock, which are further utilized to sample the data at an optimal point. Different implementation techniques of phase interpolation exist. Some are based on Delay locked loops, and others are based on the linear interpolation between two phases (typically In-phase and Quadrature-phase) of the reference clock.
A Phase Interpolator implementations based on the linear interpolation between two phases (typically In-phase and Quadrature-phase) of the reference clock are open loop systems that produce the desired phase-shifted output by controlling the bias current steered to the I and Q summing amplifiers. One important parameter of interest is the Integrated Non-linearity (INL) of the phase positions at the output of the phase interpolator with respect to the input digital codes. The INL performance is of importance as it decides how accurately and efficiently the CDR loop can lock to the correct sampling point on the received data eye-diagram. Being an open loop system, the INL of the phase interpolator is affected by various circuit and design parameters.
As the INL is affected by so many design parameters, and any adjustments of these parameters in order to get reasonable INL performance require significant design efforts with area/power penalty, it would be highly desirable to provide a closed loop calibration system to measure and correct for the INL errors.